//вынесите (k,l,m) в параметры
/*-----------------------------------------------------------------------------
v1_filter
Created (18.12.2013)
Created by Korda Dima

Version 2.1
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Verilog Student2013
-------------------------------------------------------------------------------*/
module v4_filter
#(
	parameter SIZE_ADC_DATA                                  = 11;
	parameter SIZE_FILTER_DATA                               = 25;
	parameter DELAY                                          = 14;
	parameter SIZE_AFTER_FILTER_DATA                         = 15)
//-----------------------------------------------------------------------------
(
	input  wire                                              reset,
	input  wire                                              clk,
//-----------------------------------------------------------------------------
	input wire [SIZE_ADC_DATA:0]                             input_data,
//-----------------------------------------------------------------------------
	output reg [SIZE_AFTER_FILTER_DATA:0]                    output_data);
//-----------------------------------------------------------------------------
	reg [SIZE_ADC_DATA:0]                                    signal_delay [DELAY:0];
	reg signed [SIZE_FILTER_DATA:0]                          s;
	reg [SIZE_FILTER_DATA:0]                                 r;
	reg [SIZE_FILTER_DATA:0]                                 p;
	reg [SIZE_FILTER_DATA:0]                                 d;
	reg [SIZE_FILTER_DATA:0]                                 d1;
	reg [SIZE_FILTER_DATA:0]                                 d2;
	reg [SIZE_FILTER_DATA:0]                                 d_delay;
	reg [SIZE_FILTER_DATA:0]                                 p_delay;
//-----------------------------------------------------------------------------
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
		begin
			for (integer i=0; i<=DELAY; i++)
				signal_delay[i]                          <= 0;
			output_data                                  <= 0;
			p                                            <= 0;
			s                                            <= 0;
			d                                            <= 0;
			r                                            <= 0;
			d1                                           <= 0;
			d2                                           <= 0;
			d_delay                                      <= 0;
			p_delay                                      <= 0;
		end
		else
		begin
			signal_delay[0]                              <= input_data;
			for (integer i=1; i<=DELAY; i++)
				signal_delay[i]                          <= signal_delay[i-1];
			d1                                           <= signal_delay[0] - signal_delay[9];
			d2                                           <= signal_delay[5] - signal_delay[14];
			d                                            <= d1 - d2;
			p                                            <= p + d;
			d_delay                                      <= 16 * d;
			p_delay                                      <= p;
			r                                            <= p_delay + d_delay;
			s                                            <= s + r;
			output_data                                  <= s >>>7;
			
	    end
    end
endmodule
